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SC667 7 LED Light Management Unit
POWER MANAGEMENT Features

Automatic Dropout Prevention, Ambient Light Sense Input, PWM Dimming, and 4 LDOs Description
The SC667 is a highly integrated light management unit that provides programmable current for up to seven LED current sinks. Four LED banks are provided to allow settings for various LED zones or indicators. Four low-noise LDOs with programmable outputs ranging from 1.2V to 3.3V and 200mA maximum output current are also included. ADP limits the maximum LED current to a level that ensures the LEDs maintain matched currents when the supply voltage approaches dropout. This feature produces acceptable light output at low supply voltage levels without requiring a boost converter or charge pump. Two interfaces are provided for design flexibility. The I2C interface controls the LED on/off functions, assigns the LEDs to backlight banks, programs the LED currents, programs the lighting effects, enables the LDOs, and sets the LDO output voltages. The PWM interface reduces the current setting for LED bank #1 by a factor equal to the duty cycle of the applied PWM signal. A filter at the PWM input converts the pulsed signal to a DC current level, resulting in less switching noise compared to pulsed current methods. The ADI input translates the voltage from an external ALS (Ambient Light Sensor) into a digitized code using a sigmadelta ADC. This block includes level detection to adjust the current setting of bank #1 with two different programmable levels based on the ambient light level. An interrupt output transitions low to notify the host processor that a level adjustment has been made.
SC667
VIN BL1 BL2 GND SDA SCL PWM EN ADI BYP CBYP BL3 BL4 BL5 BL6 BL7 IRQ LDO1 LDO2 LDO3 LDO4 C1 C2 C3 C4 VDD R1 Flag for ALS LDO1 LDO2 LDO3 LDO4
Seven LED backlight sinks with 32 current settings from 0mA to 25mA Up to four LED backlight banks Lighting effects -- fade-in/fade-out, breathe, blink, auto-dim full, and auto-dim partial functions ADP (Automatic Dropout Prevention) for backlights ALS (Ambient Light Sense) option sets the backlight brightness according to ambient lighting conditions I2C Bus fast mode and standard mode IRQ (Interrupt request) -- open-drain output indicates a change of state for the ALS Backlight current accuracy -- 1.5% typical Backlight current matching -- 0.5% typical Four programmable 200mA low-noise LDO regulators PWM interface (200Hz to 50kHz) with internal digital low-pass filter Automatic sleep mode with all LEDs off Shutdown current -- 0.1A typical Ultra-thin package -- 3 x 3 x 0.6 (mm) Lead-free and halogen-free WEEE and RoHS compliant
Applications

Cellular phones, smart phones, and PDAs LCD modules Portable media players and digital cameras Personal navigation devices Display/keypad backlighting and LED indicators
Typical Application Circuit
2.9 to 5.5V RSDA I2C Data I2C Clock Backlight PWM Device Enable VLDO4 RSCL VIN CIN IN
Ambient Light Sensor
May 21, 2010
(c) 2010 Semtech Corporation
1
SC667
Pin Configuration
LDO2 LDO3 LDO4
Ordering Information
Device
BYP EN
Package
MLPQ-UT-20 3x3 Evaluation Board
SC667ULTRT(1)(2) SC667EVB
20
19
18
17
16
LDO1 VIN GND PWM BL7
1 TOP VIEW 2 3 4 5 T
15 14 13 12 11
IRQ SDA SCL ADI BL1
Notes: (1) Available in tape and reel only. A reel contains 3,000 devices. (2) Lead-free package only. Device is WEEE and RoHS compliant and halogen-free.
6
7
8
9
10
BL6
BL5
BL4
BL3
MLPQ-UT-20; 3x3, 20 LEAD JA = 35C/W
Marking Information
667 yyww xxxx
yyww = Date Code xxxx = Semtech Lot Number
BL2
2
SC667
Absolute Maximum Ratings
Pin Voltage -- IN (V) . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0 Pin Voltage -- All Other Pins (V) . . . . . . . . . -0.3 to (VIN + 0.3) LDOn Short Circuit Duration . . . . . . . . . . . . . . .Continuous
(1)
Recommended Operating Conditions
Ambient Temperature Range (C) . . . . . . . . . .-40 TA +85 Input Voltage (V) . . . . . . . . . . . . . . . . . . . . . . . . .2.9 VIN 5.5 Backlight Sink Voltage (V) . . . . . . . . . . . . . . . .0.05 VBLn 4.2
ESD Protection Level (kV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5
(2)
Thermal Information
Thermal Resistance, Junction to Ambient(3) (C/W) . . . . 35 Storage Temperature Range (C) . . . . . . . . . . . . -65 to +150 Peak IR Reflow Temperature (10s to 30s) (C) . . . . . . . +260
Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not recommended. NOTES: (1) Subscripting for all LDOs (LDOn), n = 1, 2, 3, 4. (2) Tested according to JEDEC standard JESD22-A114-B. (3) Calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards.
Electrical Characteristics
Parameter
Supply Specifications Input Supply Voltage Shutdown Current
Unless otherwise noted, TA = +25C for Typ, -40C to +85C for Min and Max, TJ(MAX) = 125C, VIN = 3.7V, CIN = CLDO1 = CLDO2 = CLDO3 = CLDO4 = 1.0F, CBYP = 22nF, (ESR = 0.03)(1)
Symbol
Conditions
Min
Typ
Max
Units
VIN IQ(OFF) Shutdown, VIN = 4.2V Sleep (all LDOs off ), EN = VIN(2)
2.9 0.1 90 300 1.4
5.5 2.0 135
V A
A 450 mA
Total Quiescent Current
IQ
Sleep (all LDOs on), EN = VIN (2) 7 LEDs on
LED Sink Electrical Specifications Maximum Total Backlight Current Backlight Current Setting Range Backlight Current Accuracy Backlight Current Matching(4) Dropout Voltage(5) Current Sink Off-State Leakage Current IOUT(MAX) IBL IBL_ACC IBL-BL VDO IBL/FL(OFF) Sum of all active LED currents, VIN above dropout level Nominal setting for BL1 - BL7 IBLn (3) = 12mA IBLn (3) = 12mA One bank of 6 backlights set equal to 20mA VIN = VBLn(3) = 4.2V -3.5 0 1.5 0.5 59 0.1 1 +3.5 175 25 mA mA % % mV A
3
SC667
Electrical Characteristics (continued)
Parameter
LDO Electrical Specifications LDO1, LDO3, and LDO4 Voltage Setting Range LDO2 Voltage Setting Range VLDOm(6) VLDO2 VLDO VDm (6) VD2 Current Limit ILIM DVLINE ILDOm (6) = 1mA, VIN = 2.9V to 4.2V, VLDOm = 2.8V ILDO2 = 1mA, VIN = 2.9V to 4.2V, VLDO2 = 1.8V VLDOm (6) = 3.3V, ILDOm = 1mA to 100mA VLDO2 = 1.8V, ILDO2 = 1mA to 100mA 1.5V < VLDOm < 3.0V, f < 10kHz, CBYP = 22nF, ILDOm = 50mA, with 0.5VP-P supply ripple 1.2V < VLDO2 < 1.8V, f < 10kHz, CBYP = 22nF, ILDO2 = 50mA, with 0.5VP-P supply ripple 10Hz < f < 100kHz, CBYP = 22nF, CLDOm = 1F, ILDOm = 50 mA, 1.5V < VLDOm < 3.0V 10Hz < f < 100kHz, CBYP = 22nF, CLDO2 = 1F, ILDO2 = 50 mA, 1.2V < VLDO2 < 1.8V Nominal value for CLDOn (6) 1 Range of nominal settings Range of nominal settings ILDOn (6) = 1mA, TA = 25C, 2.9V VIN 4.2V ILDOn (6) = 1mA to 100mA, 2.9V VIN 4.2V ILDOm (6) = 150mA, VIN = VLDOm + VDm ILDO2 = 100mA, VIN = VLDO2 + VD2 200 2.1 1.3 10 8 53 dB 61 67 VRMS 47 F 7.2 mV 4.8 25 mV 20 1.5 1.2 -3 -3.5 150 100 1.0 3.3 1.8 +3 +3.5 200 mV 150 mA V V % %
Symbol
Conditions
Min
Typ
Max
Units
Output Voltage Accuracy
Dropout Voltage
Line Regulation
Load Regulation
DVLOAD
PSRRm (6) Power Supply Rejection Ratio PSRR2 en-LDOm (6) Output Voltage Noise en-LDO2 Minimum LDO Capacitor (1) ADC Specifications Resolution Offset Gain Error Integral Non-Linearity ADRES ADOFFSET ADGAIN_ERR INL CLDO(MIN)
8 VLDO4 = 3.3V VLDO4 = 3.3V VLDO4 = 3.3V 1 0.1 1
bits LSB % LSB
4
SC667
Electrical Characteristics (continued)
Parameter Symbol Conditions Min Typ Max Units
Digital Input Electrical Specifications (PWM, EN, SDA, SCL) Input High Threshold (7) (8) Input Low Threshold (7) (8) Input High Current Input Low Current VIH VIL IIH IIL VIN = 5.5V VIN = 2.9V VIN = 5.5V VIN = 5.5V -1 -1 1.6 0.4 +1 +1 V V A A
Digital Output Electrical Specification (IRQ) IRQ Output Low Level PWM Input Specification (PWM) PWM Input Frequency fPWM 0.2 50 kHz VOL IIRQ 3mA 0.4 V
I2C Interface
Interface complies with slave mode I2C interface as described by Philips I2C specification version 2.1 dated January, 2000. Digital Input Voltage (7) SDA Output Low Level Digital Input Current Hysteresis of Schmitt Trigger Inputs Maximum Glitch Pulse Rejection I/O Pin Capacitance I2C Timing Clock Frequency (7) SCL Low Period (7) (8) SCL High Period
(7) (8)
VB-IL VB-IH IDIN (SDA) 3mA IB-IN VHYS tSP CIN -0.2 0.1 50 10 1.6
0.4
V V
0.4 0.2
V A V ns pF
fSCL tLOW tHIGH tHD_DAT tSU_DAT tSU_STA tHD_STA tSU_STO tBUF tEN Bus start-up time after EN pin is pulled high 1.3 0.6 0 100 0.6 0.6 0.6 1.3
400
440
kHz s s s ns s s s s
Data Hold Time (7) (8) Data Setup Time
(7) (8)
Setup Time for Repeated START Condition (7) (8) Hold Time for Repeated START Condition (7) (8) Setup Time for STOP Condition (7) (8) Bus-Free Time Between STOP and START (7) (8) Interface Start-up Time (7) (8)
900
s
5
SC667
Electrical Characteristics (continued)
Parameter
Fault Protection Over-Temperature TOTP THYS VUVLO VUVLO-HYS Rising threshold Hysteresis Increasing VIN 165 30 2.4 500 C C V mV
Symbol
Conditions
Min
Typ
Max
Units
Under Voltage Lockout
Notes: (1) Capacitors are MLCC of X5R type. (2) EN is high for more than 10ms. (3) Subscript for all backlights (BLn), n = 1, 2, 3, 4, 5, 6, and 7. (4) Current matching is defined as [IBL(MAX) - IBL(MIN)] / [IBL(MAX) + IBL(MIN)]. (5) VDO is defined as the voltage at the BLn pin when current has dropped from the target value by 10%. (6) Subscript m = 1, 3, and 4 and applies only to LDO1, LDO3, and LDO4. Subscripting for all LDOs (LDOn), n = 1, 2, 3, 4. (7) The host processor must meet these limits. (8) Guaranteed by design.
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SC667
Typical Characteristics -- Backlights
Backlight Efficiency (7 LEDs)
100 = (PLED1-7)/(VIN x IIN + VA x IA), IOUT = 7 x IBL, VA = VIN, TA = 25C VF = 3.24V IBL = 25mA IBL = 12mA Efficiency (%) 80 VF = 2.80V 70 IBL = 5mA IBL = 1mA 60 IBL = 0.5mA 50 4.2 3.9 3.6 VIN (V) 3.3 3.0 2.7 1.0 4.2 3.9 3.6 VIN (V) 3.3 3.0 2.7 VF = 2.74V 1.1 VF = 2.97V IIN (mA) 1.3 IBL = 12 mA, VF = 3.10V IBL = 5 mA, VF = 2.97V IBL = 1 mA, VF = 2.80V IBL = 0.5 mA, VF = 2.74V VF = 3.10V 1.4 IBL = 25 mA, VF = 2.24V 3.24V 1.5
Supply Current (7 LEDs)
I OUT = 7 x IBL, VA = VIN , TA = 25C
90
1.2
Dropout Voltage VDO vs IBL (6 LEDs)
80 70 60 TA=85C VDO = VBLn when IBLn has dropped 10% from the target value
TA=25C
VDO (mV)
50 40 30 20 10 TA=-40C
0
5
10 15 IBLSetting (mA)
20
25
7
SC667
Typical Characteristics -- Backlights (continued)
Group #1 Blink Function (25mA)
Start time = 32ms, target time = 3072ms
Group #1 Breathe Function (20mA to 0.5mA)
Breathe rate = 24ms, start time = 32ms, target time = 1024ms
-- 25mA
-- 20mA IBL (10mA/div) 0mA IBL (10mA/div) -- 0.5mA
Time (400msdiv) sdiv) div)
Time (1000msdiv) sdiv) div)
Bank #1 with ADP (rate = 256s)
Battery transient condition: 100Hz, 12.5% duty cycle
Backlight with ADP (rate = 4ms)
Battery transient condition: 50Hz, 30% duty cycle
IBL (10mA/div)
15mA 15mA 0mA
11mA
IBL (10mA/div)
15mA 14
13
12
11
10
9
8mA
3.40V VIN (500mV/div) 3.05V VIN (500mV/div)
3.32V
2.98V Time (20msdiv) sdiv) div)
Time (10msdiv) sdiv) div)
Backlight Dimming with ALS and Fade
VIN = 3.7V, VLDO4 = 2.8V, ADRISE = B0h, ADFALL = 80h, 4ms fade rate
IBL (10mA/div) 0mA -- 2.8V -- VADI (1V/div) 0V -- 0.5mA
10mA 0.5mA ADC reference brighter ambient lighting dimmer
Time (1000msdiv) sdiv) div)
8
SC667
Typical Characteristics -- LDOs
Load Regulation (LDO2)
0 VIN = 3.7V, TA = 25C
0
Load Regulation (LDOm)
VIN = 3.7V, m = 1, 3, or 4, TA = 25C
1.2V
Output Voltage Variation (mV)
1.5V
Output Voltage Variation (mV)
-5
1.5V
-5
1.8V 2.5V
-10 1.8V -15
-10
-15
2.8V 3.3V
-20
-20
-25
0
40
80
ILDO (mA)
120
160
200
-25
0
40
80
ILDO (mA)
120
160
200
Line Regulation (LDO2)
1 0.75 ILDO2 = 1mA, VLDO2 = 1.2V to 1.8V, TA = 25C
Line Regulation (LDOm)
3 2 ILDOm = 1mA, VLDOm = 1.5V to 3.3V, m = (1,3, or 4), TA = 25C
Output Voltage Variation (mV)
0.5 0.25 0 1.2V 1.8V
Output Voltage Variation (mV)
1 0 3.3V -1 2.8V
-0.25 -0.5
1.5V 1.8V
-0.75 -1
-2 -3
4.20
3.90
3.60 VIN (V)
3.30
3.00
2.70
4.20
3.90
3.60
VIN (V)
3.30
3.00
2.70
LDO Noise vs. Load Current (1.8V)
100 VLDO = 1.8V, VIN = 3.7V, 10Hz < f < 100kHz, TA = 25C 100
LDO Noise vs. Load Current (2.8V)
VLDO = 2.8V, VIN = 3.7V, 10Hz < f < 100kHz, TA = 25C
80
80
Noise (VRMS)
Noise (VRMS ) 0 40 80 120 160 200
60
60
40
40
20
20
0
0
IOUT (mA)
0
40
80
IOUT (mA)
120
160
200
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SC667
Typical Characteristics -- LDOs (continued)
PSRR vs. Frequency (1.8V)
0 -10 -20
PSRR (dB)
PSRR vs. Frequency (2.8V)
0 -10 -20
PSRR (dB)
VIN = 3.7V, VLDOn = 1.8V, ILDOn = 50mA
VIN = 3.7V, VLDOn = 2.8V, ILDOn = 50mA
-30 -40 -50 -60 -70
-30 -40 -50 -60 -70
10
100
Frequency (Hz)
1000
10000
10
100
Frequency (Hz)
1000
10000
Load Transient Response (1.2V)
VIN = 3.7V, VLDO = 1.2V, ILDO = 1mA to 200mA, TA = 25C
Load Transient Response (1.8V)
VIN = 3.7V, VLDO = 1.8V, ILDO = 1mA to 200mA, TA = 25C
VLDO (50mV/div)
VLDO (50mV/div)
200mA ILDO (100mA/div) 0mA ILDO (100mA/div) 0mA
200mA
Time (20sdiv) sdiv) div)
Time (20sdiv) sdiv) div)
Load Transient Response (3.3V)
VIN = 3.7V, VLDO = 3.3V, ILDO = 1mA to 200mA, TA = 25C
VLDO (50mV/div)
200mA ILDO (100mA/div) 0mA
Time (20sdiv) sdiv) div)
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SC667
Pin Descriptions
Pin #
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 T
Pin Name
LDO1 VIN GND PWM BL7 BL6 BL5 BL4 BL3 BL2 BL1 ADI SCL SDA IRQ EN BYP LDO4 LDO3 LDO2 THERMAL PAD
Pin Function
LDO1 output Battery voltage input Ground pin Backlight PWM control signal input Current sink output for backlight LED 7 -- leave this pin open if unused Current sink output for backlight LED 6 -- leave this pin open if unused Current sink output for backlight LED 5 -- leave this pin open if unused Current sink output for backlight LED 4 -- leave this pin open if unused Current sink output for backlight LED 3 -- leave this pin open if unused Current sink output for backlight LED 2 -- leave this pin open if unused Current sink output for backlight LED 1 -- leave this pin open if unused ADC input I2C clock input I2C data -- bi-directional line used for read and write operations for all internal registers (refer to Register Map and I2C Interface sections) Interrupt request -- open-drain output, active-low Chip enable -- active high Bypass pin for LDO reference -- connect a 22nF ceramic capacitor to GND LDO4 output LDO3 output LDO2 output Thermal pad for heatsinking purposes -- connect to ground plane using multiple vias -- not connected internally
11
SC667
Block Diagram
VIN IN GND PWM 2 3 4 Digital LP Filter Current sink control block 5 6 7 8 9 10 11 VIN VLDO_REF VIN Register Space Digital Interface Logical Control LDO DAC Backlight DAC LDO1 1 LDO1 17 BYP BL7 BL6 BL5 BL4 BL3 BL2 BL1
EN
16
SDA SCL
14 13
I2C Interface
Reg (00h) to Reg (16h)
VIN LDO2 20 LDO2
VIN LDO3 19 LDO3
ADRISE ADFALL ADOUT
VIN VLDO4 ADI 12 ADC IRQ LDO4 18 LDO4
15 logical state of bit AD_INT
12
SC667
Applications Information
General Description
The SC667 is optimized for handheld applications supplied from a single cell Li-Ion and includes the following key functions: forward voltage of the LEDs is available. The resulting efficiency in this scenario would be optimal. To achieve best accuracy, the current sink amplifier requires the LED sink pin (BLn) to be within the operational range of VDO VBLn 4.2V. When the sink is off, VBLn may float as high as 5.5V.
VIN IN CIN
* * * * *
Seven matched current sinks -- BL1, BL2, BL3, BL4, BL5, BL6, and BL7 regulate LED backlighting current, with 0mA to 25mA per LED. Four adjustable LDOs -- LDO1, LDO3, and LDO4 are adjustable with 15 settings from 1.5V to 3.3V. LDO2 is adjustable with 7 settings from 1.2V to 1.8V. ALS with a sigma-delta ADC that can also be used for general purpose ADC functions. PWM with an internal digital low-pass filter I2C Bus fast mode and standard mode
SC667
BL1 BL2 BL3 BL4 BL5 BL6 BL7
VBL1 VBL2 VBL3 VBL4 VBL5 VBL6 VBL7
VA
GND
LED Backlight Current Settings
The backlight current is set via the I2C interface. The current is regulated to one of 32 values between 0mA and 25mA. The step size varies depending upon the current setting. The first three steps are 50A, 100A, and 200A. Between 0.5mA and 5mA, the step size is 0.5mA. The step size increases to 1mA for settings between 5mA and 21mA. Steps are 2mA between 21mA and 25mA. The variation in step size allows finer adjustment for dimming functions in the low current range and coarse adjustment at higher current settings where larger changes are not visible. The settings are psuedo-logarithmic. A zero setting also disables the current sink, providing an alternative to the enable bit.
Figure 1 -- Anode Supply
Unused Backlight Current Sinks
The backlight LEDs default to the off state upon powerup. For backlight applications using fewer than 7 LEDs, any unused output must be left open or grounded and the unused LED must remain disabled. When writing to the backlight enable register, a zero (0) must be written to the corresponding enable bit of any unused output.
Backlight Quiescent Current
The quiescent current required to operate the backlights is reduced when backlight current is less than 8.0mA. This feature results in higher efficiency under light-load conditions. Further quiescent current reduction will result from using fewer LEDs.
LED Backlight Current Sinks
Backlight current is independent of forward voltage mismatch (VF) between LEDs. When two or more backlight sinks are set to the same target current, their currents will match, even if the LED voltages are different. The backlight current sinks are designed with a low dropout voltage (typically 59mV for a bank of 6 LEDs at 20mA) to optimize run-time when the LED anode voltage is provided by a battery.
Backlight Configuration into Banks
The seven LED backlight drivers can be assigned to a single bank or divided among up to four independent banks -- refer to the Register Map section for more details. The independent banks can each be configured with different settings for backlight current and fade operation.
LED Anode Supply
In the typical application circuit, the battery voltage supplies the LEDs. An alternative to this configuration is to connect the LED anodes to a second DC supply as shown in Figure 1. Such a connection is especially useful when an alternate voltage that is slightly higher than the
Bank Configuration into Groups
The four backlight banks can be assigned to two groups (group #1 and group #2). Each group provides independent settings for the fade and breathe effect rate options. Each group also provides independent settings for target time and start time, which are used to customize the
13
SC667
Applications Information (continued)
blink and breathe lighting effects. Details of the fade, breathe, and blink effects are introduced later in this Applications Information section. time parameter. When the start time has ended, the breathe cycle begins again. The breathe effect rate is programmable for group #1 and group #2 and can be independently set to 4, 8, 16, 24, 32, 48, or 64ms for each group. Also, the start time and target time parameters for group #1 and group #2 can be independently set to 32, 64, 256, 512, 1024, 2048, 3072, or 4096ms. In addition to the group's timing parameters, start current and target current values and BxBEN (blink/breathe enable) and BxFEN (fade enable) bits are set for each bank to define that bank's min and max current during a breathe cycle and enable the breathe function. The five parameters that define the breathe effect are: 1. Effect rate -- write value to register 0Fh 2. Start current -- write value to register 02h, 03h, 04h, or 05h (bank dependent) 3. Target current -- write value to registers 06, 07h, 08h, or 09h (bank dependent) 4. Start time -- write value to register 10h or 11h (group dependent) 5. Target time -- write to register 10h or 11h (group dependent Figure 3 illustrates the breathe effect with respect to time. For an example of the breathe effect, with bank #1 assigned to group #1, the terms used in the illustration are as follows:
Target Backlight Settings for Lighting Effects
The target backlight setting is the current which will result at the end of a blink or breathe lighting effect cycle. The Register Map contains four control registers which set the target backlight currents for each bank. Registers 06h, 07h, 08h, and 09h contain the target current values for: bank #1, bank #2, bank #3, and bank #4, respectively. Bank #1 also uses the target value of register 06h in association with the ALS function. Bank #1 can be set to automatically change to the target value of register 06h when the ADC exceeds a programmable rising threshold. ALS is defined in more detail under Ambient Light Sense, and in the Register Map section under ADC Function Register 12h.
Breathe Lighting Effect
The breathe lighting effect may be applied independently to each group. When this feature is enabled, the bank's backlight current will increase and decrease periodically at a rate that mimics calm and smooth breathing. Once initialized via the I2C interface, this function will run continuously, independent of the host processor, saving instruction cycles and simplifying timing requirements. Three timing parameters must be set to define the breathe effect timing: effect rate, start time, and target time. Group #1 and group #2 have independent timing parameters to support a variety of options. When a bank is assigned to a group, it adopts the timing parameters of the respective group. When enabled, the breathe function causes the backlights to change brightness by stepping the current incrementally, using the effect rate parameter, until the final backlight current is reached. The current will remain at the target value for a time set by the target time parameter. When the target time has ended, the brightness will again change, this time in reverse order, stepping the current incrementally, using the effect rate parameter, until the current returns to the start value. The current will remain at the start value for the time set by the start
* * * * *
IBL_START = contents of register 02h (B1FEN must equal 1) IBL_TARGET = contents of register 06h (B1BEN must equal 1) tSTART = contents of bits ST1_[2:0] in register 10h tTARGET = contents of bits TT1_[2:0] in register 10h tBREATHE = breathe time. Equal to the breathe rate times the number of steps between IBL_START and IBL_TARGET. Breathe time is set with the bits ER1_ [2:0] in register 0Fh.
Blink Lighting Effect
The blink lighting effect provides an automatic LED blinking function that can be applied to a single LED driver or
14
SC667
Applications Information (continued)
an LED driver bank without any host processor interaction. Blinking can be initialized via the I2C interface at power up and the settings maintained in the SC667 registers with no need for additional software interaction. Two timing parameters must be set to define the blink effect timing: start time and target time. Start and target times can be independently set to 32, 64, 256, 512, 1024, 2048, 3072, 4096ms. The total blink cycle time is equal to the sum of the start and target times. In addition to timing parameters, start current and target current values are used to set the bank's min and max current, and a combination of bits BxBEN (blink/breathe enable) and BxFEN (fade enable) are used to enable the blink function. The four parameters are: 1. Start current -- write value to register 02h, 03h, 04h, or 05h (bank dependent) 2. Target current -- write value to register 06, 07h, 08h, or 09h (bank dependent) 3. Start time -- write value to register 10h or 11h (group dependent) 4. Target time -- write to register 10h or 11h (group dependent) Figure 4 illustrates the blink effect with respect to time. For an example of the blink effect, with bank #2 assigned to group #2, the terms used in the illustration are as follows: group #1 and group #2 and can be independently set to 1, 2, 4, 6, 8, 12, or 16ms for each group. The fade function causes the bank to begin stepping from its current state to the next programmed state as soon as the new state is stored in its register. For example, if the bank is set to 25mA, fade is enabled, and the bank is changed to 0mA, the bank will step from 25mA down to 0mA using all settings between 25mA and 0mA. In addition to the 32 programmable backlight current values, there are also 75 non-programmable current steps. The non-programmable steps are active only during a fade or breathe operation to provide for a very smooth change in backlight brightness. Backlight current steps proceed at a programmable fade rate of 1, 2, 4, 6, 8, 12, or 16ms. The exact length of time used to fade between any two backlight values is determined by multiplying the fade rate by the number of steps between the old and new backlight values. The fade time can be calculated from the data provided in Table 1 on page 19. Two parameters must be programmed to enable the fade effects: effect rate and start current. The fade function will begin when a new start current is set along with the FEN bit in the associated register. The fade effect rate parameter must be set to define the fade timing. Group #1 and group #2 have independent sets of timing parameters to support a variety of fade timing options. When a bank is assigned to a group, it adopts the timing parameters of the respective group. Registers associated with fade are described below: 1. Effect Rate -- write a value to register 0Fh (group dependent) 2. Start Current -- write value to register 02h, 03h, 04h, or 05h (bank dependent) Figure 5 illustrates the fade-in and fade-out effects with respect to time. For an example of the fade effects assigned to bank 3 with effect rate 2, the terms in the illustration are as follows:
* * * *
IBL_START = contents of register 03h (B2FEN must equal 0) IBL_TARGET = contents of register 07h (B2BEN must equal 1) tSTART = contents of bits ST2_[2:0] in register 11h tTARGET = contents of bits TT2_[2:0] in register 11h
Backlight Fade-In and Fade-Out Lighting Effects
When enabled, the fade function causes the backlights to change brightness by stepping the current incrementally until the final backlight current is reached. The backlight fade-in and fade-out may be applied to selected banks. When enabled, the bank current will gradually increase during fade-in and gradually decrease during fade-out. The rate of increase or decrease is programmable for
*
IBL_INITIAL = contents of register 04h (B3FEN must equal 1)
15
SC667
Applications Information (continued)
* * *
IBL_FINAL = new value written to register 04h (register 07h bit B3BEN must equal 0), however, the "Target" value of register 07h has no effect on fade. tFADE_IN = contents of bits ER2_[2:0] in register 0Fh tFADE_OUT = tFADE_IN
occur immediately. When changing brightness without effects, registers 02h through 05h are used for this function. The target values of registers 06h through 09h are not involved. Figure 8 illustrates the brightness change with respect to time. An example of brightness change to bank #4 with no lighting effect, is as follows:
Auto-Dim Lighting Effect
Two auto-dim settings are provided -- auto-dim full and auto-dim partial. These settings provide automatic dimming of bank #1. The auto-dim delay times are set using the group #1 target and start time register (10h). Delay times are 8 times the group #1 target and start times. Auto-dim full provides a time-out and dimming function followed by a time-out and turn-off function. Auto-dim full begins when the bank is enabled (or re-enabled), the bank will first go to the target current and wait for a count of 8 times the group #1 target time. The bank will then dim to the "start" current and wait for a count of 8 times the group #1 start time. The bank will then turn off. Auto dim partial provides the time-out and dimming function, but does not turn off backlights. Auto-dim partial begins when the bank is enabled (or re-enabled), the bank will first go to the target current and wait for a count of 8 times the group #1 target time. The bank will then dim to the "start" current. The bank will not turn off automatically. Auto-dim is available only for group #1. After selecting an auto-dim option, the bank's blink effect must be enabled to enable auto-dim. The bank must then be enabled or reenabled to begin the auto-dim. Auto-dim partial is illustrated in Figure 6, and auto-dim full is illustrated in Figure 7.
* *
IBL_INITIAL = previous value written to register 05h IBL_FINAL = new value written to register 05h
The register 05h bit B4FEN must equal 0, and register 09h bit B4BEN must equal 0, however, the "Target" value of register 09h has no effect on the final current.
Fade State Diagram
The state diagram in Figure 2 describes the fade operation. If the backlight enable bits are disabled during an
No change Immediate change to new bright level
Write BxFEN=0
BxFEN=0
Write new bright level
Write BxFEN=1
Immediate change to new bright level
Write BxFEN=0 No change
BxFEN=1
Write BxFEN=0 or Write {0,0,0} to effect rate bits register 0Fh Write BxFEN=1 Write new bright level Fade ends Fade begins Fade begins at 0mA Fade is redirected toward the new value from current state Write new bright level Continue fade using new rate Write entire bank's enable bits BLxEN = 0 Write BLxEN = 1
Brightness Change without Effects
There are two ways to change brightness while using no lighting effect. One way is to set the effect rate option to the zero value "snap to target" (a function of register 0Fh). This method will block all lighting effects on all banks within a group. Another way to change brightness, with no lighting effect, is to set the BxFEN and BxBEN both equal to zero. This second method will block all lighting effects on a single bank, and with no influence over other banks within the group. Writing a new value to the backlight current register, while effects are disabled, will cause the change in brightness to
No change
Fade processing
Write BxFEN=1
Bank turns off immediately
Backlights disabled
Write new fade rate
Figure 2 -- State Diagram for Fade Function
16
SC667
Applications Information (continued)
tTARGET tBREATE IBL_START tSTART
0mA
tTARGET
IBL_TARGET
t1
t2
Figure 3 -- Breathe Timing Diagram
tTARGET
IBL_START tSTART
IBL_TARGET
0mA
t1
t2
Figure 4 -- Blink Timing Diagram
tFADE_OUT
tFADE_IN
IBL_INITIAL
IBL_FINAL
IBL_INITIAL
IBL_FINAL
0mA
t1
t2
Figure 5 -- Fade-in and Fade-out Timing Diagram
tTARGET
Bank enabled/ re-enabled
IBL_TARGET Bank does not turn off automatically IBL_START
0mA
Figure 6 -- Auto-Dim Partial Timing Diagram
tTARGET
Bank enabled/ re-enabled
IBL_TARGET
IBL_START
0mA
tSTART
Figure 7 -- Auto-Dim Full Timing Diagram
Note: See next page for figure notes.
IBL_FINAL
IBL_INITIAL
IBL_FINAL
IBL_INITIAL
0mA
Figure 8 -- Brightness Increase and Decrease Without Fade Timing Diagram
17
SC667
Applications Information (continued)
Notes for figures on previous page t1 = start of cycle t2 = end of cycle tSTART = The time that the bank's current remains at the start value. tTARGET = The time that the bank's current remains at the target value. tBREATHE = The time that the bank's current will continue to increase or decrease during a breathe cycle. Breathe time is determined by multiplying the breathe rate by the number of steps (from Table1). Breathe rate is a group dependent value of the effect rate register 0Fh. tFADE_IN = The fade time of increasing bank current, determined by multiplying the fade rate by the number of steps (from Table 1). Fade rate is a group dependent value of the effect rate register 0Fh. tFADE_OUT = The fade time of decreasing bank current, determined by multiplying the fade rate by the number of steps (from Table 1). Fade rate is a group dependent value of the effect rate register 0Fh. tFADE_IN is always equal to tFADE_OUT. IBL_START = The bank current at the start of the cycle. This is the bank dependent value of register 02h, 03h, 04h, or 05h. IBL_TARGET = The bank current at the end of the cycle. This is the bank dependent value of register 06h, 07h, 08h, or 09h. IBL_INITIAL = The bank dependent value of register 02h, 03h, 04h, or 05h. IBL_FINAL = The bank dependent value of register 02h, 03h, 04h, or 05h. NOTE: "START" and "TARGET" subscripts apply only to blink and breathe effects which require a target value to complete a cycle. "INITIAL" and "FINAL" subscripts apply when changing a bank's current without use of the target registers.
18
SC667
Applications Information (continued)
Table 1 -- Number of Backlight Fade / Breathe Steps between Values (See Note)
25 106 105 104 102 96 23 102 101 100 98 21 20 19 18 17 16 15 14 13 12 11 10 9 8 98 96 94 92 90 88 86 84 82 80 76 72 68 64 59 54 46 42 38 34 30 26 22 18 14 10 4 2 1 0 97 95 93 91 89 87 85 83 81 79 75 71 67 63 58 53 45 41 37 33 29 25 21 17 13 9 3 1 0 1 96 94 92 90 88 86 84 82 80 78 74 70 66 62 57 52 44 40 36 32 28 24 20 16 12 8 2 0 1 2 94 92 90 88 86 84 82 80 78 76 72 68 64 60 55 50 42 38 34 30 26 22 18 14 10 6 0 2 3 4 92 88 86 84 82 80 78 76 74 72 70 66 62 58 54 49 44 36 32 28 24 20 16 12 8 4 0 6 8 9 10 90 86 82 80 78 76 74 72 70 68 66 64 62 58 54 50 45 40 32 28 24 20 16 12 8 4 0 4 10 12 13 14 88 84 80 78 76 74 72 70 68 66 64 62 58 54 50 46 41 36 28 24 20 16 12 8 4 0 4 8 14 16 17 18 84 80 76 74 72 70 68 66 64 62 60 58 54 50 46 42 37 32 24 20 16 12 8 4 0 4 8 12 18 20 21 22 80 76 72 70 68 66 64 62 60 58 56 54 50 46 42 38 33 28 20 16 12 8 4 0 4 8 12 16 22 24 25 26 76 72 68 66 64 62 60 58 56 54 52 50 46 42 38 34 29 24 16 12 8 4 0 4 8 12 16 20 26 28 29 30 72 68 64 62 60 58 56 54 52 50 48 46 42 38 34 30 25 20 12 8 4 0 4 8 12 16 20 24 30 32 33 34 68 64 60 58 56 54 52 50 48 46 44 42 38 34 30 26 21 16 8 4 0 4 8 12 16 20 24 28 34 36 37 38 64 60 56 54 52 50 48 46 44 42 40 38 34 30 26 22 17 12 4 0 4 8 12 16 20 24 28 32 38 40 41 42 60 56 52 50 48 46 44 42 40 38 36 34 30 26 22 18 13 8 0 4 8 12 16 20 24 28 32 36 42 44 45 46 52 48 44 42 40 38 47 43 39 37 35 33 42 38 34 32 30 28 26 24 22 20 18 16 12 8 4 0 5 10 18 22 26 30 34 38 42 46 50 54 60 62 63 64 38 34 30 28 26 24 22 20 18 16 14 12 8 4 0 4 9 14 22 26 30 34 38 42 46 50 54 58 64 66 67 68 34 30 26 24 22 20 18 16 14 12 10 8 4 0 4 8 13 18 26 30 34 38 42 46 50 54 58 62 68 70 71 72 30 26 22 20 18 16 14 12 10 8 6 4 0 4 8 12 17 22 30 34 38 42 46 50 54 58 62 66 72 74 75 76 26 22 18 16 14 12 10 8 6 4 2 0 4 8 12 16 21 26 34 38 42 46 50 54 58 62 64 70 76 78 79 80 24 20 16 14 12 10 8 6 4 2 0 2 6 10 14 18 23 28 36 40 44 48 52 56 60 64 66 72 78 80 81 82 22 18 14 12 10 8 6 4 2 0 2 4 8 12 16 20 25 30 38 42 46 50 54 58 62 66 68 74 80 82 83 84 20 16 12 10 8 6 4 2 0 2 4 6 10 14 18 22 27 32 40 44 48 52 56 60 64 68 70 76 82 84 85 86 18 14 10 8 6 4 2 0 2 4 6 8 12 16 20 24 29 34 42 46 50 54 58 62 66 70 72 78 84 86 87 88 16 12 8 6 4 2 0 2 4 6 8 10 14 18 22 26 31 36 44 48 52 56 60 64 68 72 74 80 86 88 89 90 14 10 6 4 2 0 2 4 6 8 10 12 16 20 24 28 33 38 46 50 54 58 62 66 70 74 76 82 88 90 91 92 12 8 4 2 0 2 4 6 8 10 12 14 18 22 26 30 35 40 48 52 56 60 64 68 72 76 78 84 90 92 93 94 10 6 2 0 2 4 6 8 10 12 14 16 20 24 28 32 37 42 50 54 58 62 66 70 74 78 80 86 92 94 95 96 8 4 0 2 4 6 8 10 12 14 16 18 22 26 30 34 39 44 52 56 60 64 68 72 76 80 82 88 94 4 0 4 6 8 10 12 14 16 18 20 22 26 30 34 38 43 48 56 60 64 68 72 76 80 84 86 92 0 4 8 10 12 14 16 18 20 22 24 26 30 34 38 42 47 52 60 64 68 72 76 80 84 88 90 96
36 31 34 32 30 28 26 22 18 14 10 5 0 8 12 16 20 24 28 32 36 40 44 50 52 53 54 29 27 25 23 21 17 13 9 5 0 5 13 17 21 25 29 33 37 41 45 49 55 57 58 59
Starting Value (mA)
7 6 5 4.5 4 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.2 0.1 0.05 0.0
98 102
96 100 104 97 101 105 98 102 106
0.0 0.5 0.1 0.2 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 14.0 15.0 16.0 17.0 18.0 19.0 20.0 21.0 23.0 25.0
Ending Value (mA)
NOTE The fade time is determined by multiplying the number of steps by the fade rate (fade steps x fade rate = fade time). The breathe time is determined by multiplying the number of steps by the breathe rate (breathe steps x breathe rate = breathe time).
19
SC667
Applications Information (continued)
ongoing fade, the bank will turn off immediately. When the backlight bits are re-enabled and BxFEN = 1, the backlight currents will begin at 0mA and fade to the value determined by the backlight current register bits IBx[4:0]. If the backlight enable bits are re-enabled and BxFEN = 0, the main backlights will proceed immediately to the value of IBx[4:0]. Note that the words "target value" are not used to describe the final value after a fade operation. "Target value" is reserved for describing the backlight settings at the end of the blink or breathe effect cycles. the duty cycle to a DC current level. A DC current is passed through the LEDs, providing lower noise compared to the more conventional pulsed current PWM method.
PWM Sampling
The sampling system that translates the PWM signal to a DC current requires the PWM pin to have a minimum high time tHIGH_MIN to set the DC level. High time less than tHIGH_MIN impacts the accuracy of the target IBL. The minimum duty cycle needed to support the minimum high time specification varies with the applied PWM frequency (see Figure 9). Note that use of a lower PWM frequency, from 200Hz to 10kHz, will support a lower minimum duty cycle and an extended backlight dimming range.
5 tHIGH_MIN = 1s
Non-Programmable Backlight Steps
In addition to the 32 programmable backlight steps, there are 75 non-programmable steps which are used only during a fade or breathe operation. Table 1 provides the total number of steps between the starting and ending value of any fade or breathe operation. The value from Table 1 is multiplied by the fade rate to determine the total fade time. The maximum possible fade-in duration, from 0mA to 25mA, or fade-out duration, from 25mA to 0mA, is equal to 106 x 16ms = 1696ms. Figures 10 through 14 provide additional information about the non-programmable steps. Each figure represents one linear segment of the overall fade range shown in Figure 15. The overall fade range is a piece-wise linear approximation of a logarithmic function which provides for a very smooth visual fading or breathing effect. The fade rate may be changed dynamically when a fade operation is active by writing new values to the fade register. When a new backlight level is written during an ongoing fade operation, the fade will be redirected to the new value from the present state. An ongoing fade operation may be cancelled by disabling fade, which will result in the backlight current changing immediately to the final value. If fade is disabled, the current level will change immediately to the final value without the fade delay.
4
Minimum Duty Cycle (%)
3
2
1
0
0.2
10
20
30
40
50
PWM Frequency (kHz)
Figure 9 -- Minimum Duty Cycle
Ambient Light Sense
The SC667 includes a general purpose sigma-delta ADC that is designed to interface with an ambient light sensor. The ADC input accepts the output of an external ambient light sensor circuit. When the ADC is enabled via the I2C bus, the analog signal produced by the ambient light sensor is compared with two user programmable threshold levels. The result of the comparison is then used to automatically change the brightness of the LEDs in bank #1 to a user defined value. This function is used to compensate for ambient lighting conditions -- increasing brightness where brighter ambient conditions exist and decreasing brightness in lower lighting conditions.
PWM Operation on Bank #1
A PWM signal on the PWM pin can be used to adjust the DC current through the LEDs in bank #1. When the duty cycle is 100%, the backlight current through each LED (IBL) equals the full scale current value set for bank #1. The PWM input samples voltage at the PWM pin and converts
20
SC667
Applications Information (continued)
NOTES:
0.5
* = Programmable backlight steps, = Non-programmable fade/breathe steps
12 11
IBL (mA)
0.4
IBL (mA)
0.3
10
0.2
0.1
9
0.0
0
2
4
Step Count
6
8
10
8
64
68
72 Step Count
76
80
Figure 10 -- Backlight Steps (0.0mA to 0.5mA)
6.0 5.0 4.0
IBL (mA)
Figure 13 -- Backlight Steps (8.0mA to 12.0mA)
27
24
3.0 2.0 1.0 0.0 10
IBL (mA)
21
18
15
20
30
40 Step Count
50
60
12 80
85
90
95 Step Count
100
105
110
Figure 11 -- Backlight Steps (0.5mA to 6.0mA)
8.0
Figure 14 -- Backlight Steps (12.0mA to 25.0mA)
25
7.5
20
IBL (mA)
7.0
6.5
IBL (mA)
15
10
5
6.0 54
56
58 60 Step Count
62
64
0
0
20
40
60 Step Count
80
100
120
Figure 12 -- Backlight Steps (6.0mA to 8.0mA)
Figure 15 -- Backlight Steps (0.0mA to 25.0mA)
21
SC667
Applications Information (continued)
General Purpose ADC
The ADI pin may also be used for general purpose ADC functions. For example, a linear temperature sensor may be added to the application circuit, and the SC667 may provide temperature data or an over-temperature warning flag. In this case, registers 13h, 14h, and 15h can be used to store the ADC reading and set thresholds that will trigger and interrupt output if the reading does not remain between them. have identical specifications, with a programmable output ranging from 1.5V to 3.3V. LDO2 is specified to operate with programmable output ranging from 1.2V to 1.8V. All of the LDOs are low noise and can be used with noise sensitive circuits. LDO4 is internally connected to the ADC (Analog to Digital Converter) to provide the reference voltage for the ADC. LDO4 must be enabled for the ADC to function. When the ALS function is used, LDO4 may also be used to provide power to the external ALS circuit.
IRQ Output
A hardware interrupt request function is provided by the IRQ pin. This is an open-drain, active-low output that provides a flag indicating that the ALS input has exceeded a threshold level, or indicates that an overflow or underflow condition exists. Refer to Figure 16 for a description of this function.
Shutdown Mode
The device is disabled when the EN pin is held low for the shutdown time specified in the electrical characteristics section. All registers are reset to default conditions at shutdown. Typical current consumption in this mode is 0.1A.
Interrupt is set AD_INT 1 and VIRQ 0 Volts at the IRQ pin
Sleep Mode
Sleep mode is activated when all backlights are off. This is a reduced current mode that helps minimize overall current consumption. In sleep mode, the I2C interface continues to monitor its input for commands from the host processor. All registers retain their settings in sleep mode. Typical current consumption in this mode is 90A.
Bit AD_CMP changes state
AD_OF = 1 or AD_UF = 1 and AD_SATEN 01
AD_SATEN = 1 and AD_OF 01 or AD_UF 01 AD_SATEN = 0
Read register 12h or Write CLR_INT = 1
Protection Features
The SC667 provides OT (Over-temperature) protection and LDO current limiting to safeguard the device from catastrophic failures. Over-Temperature Protection The OT protection circuit prevents the device from overheating and experiencing a catastrophic failure. When the junction temperature exceeds 165C, the device goes into thermal shutdown with all outputs disabled until the junction temperature is reduced. All register information is retained during thermal shutdown. Hysteresis of 30C is provided to ensure that the device cools sufficiently before re-enabling. LDO Current Limit The device limits current at each LDO output pin. The typical limit is 400mA, with a minimum limit rating of 200mA. The LDOs may be used for up to 200mA without tripping the current limit.
22
Interrupt is reset AD_INT 0 and VIRQ VDD at the IRQ pin
Figure 16 -- IRQ Pin State Diagram
Programmable LDO Outputs
Four LDO (low dropout) regulators are included to supply power to peripheral circuits. Each LDO output voltage setting has 3.5% accuracy over the line, load, and operating temperature ranges. Output current greater than specification is possible at somewhat reduced accuracy (refer to the typical characteristic section of this datasheet for load regulation examples). LDO1, LDO3, and LDO4
SC667
Applications Information (continued)
Thermal Management
A junction temperature calculation should be performed for each new application design to ensure the device will not exceed 125C during normal operation. The first step is to determine how much power can be dissipated by the SC667 in the application. The following formula approximates the maximum dissipation. This formula can be used to sum the maximum internal power dissipation required of each LDO and each backlight sink.
PD
4 n1
( VIN VLDOn ) ILDOn
7 m1
VBLm IBLm
The resulting power dissipation can then be used in the calculation for maximum junction temperature.
TJ
where,
TA
JA
PD
TA = Maximum ambient temperature rating in C. QJA= Thermal resistance, from junction to ambient, equal to 35C/W for a optimum circuit board layout.
23
SC667
Applications Information (continued)
PCB Layout Considerations
The layout diagram in Figure 17 illustrates a two-layer PCB layout for the SC667 and supporting components. Following fundamental layout rules is critical for achieving the performance specified in the Electrical Characteristics table. The following guidelines are recommended when developing a PCB layout:
* *
Figure 18 shows the component copper layer. Make all ground connections to a solid ground plane as shown in Figure 19. All LDO output traces should be made as wide as possible to minimize resistive losses.
* * * *
Place all bypass and decoupling capacitors -- CIN, CLDO1, CLDO2, CLDO3, CLDO4, and CBYP as close to the device as possible. Ensure that all connections to pins IN and OUT make use of wide traces so that the resistive drop on each connection is minimized. The thermal pad should be connected to the ground plane using multiple vias to ensure proper thermal connection for optimal heat transfer. C LDO1, C LDO2, C LDO3, C LDO4, and C BYP should be grounded together. Connect these capacitors to the ground plane at one point near the SC667 as shown in Figure 17. Figure 18 -- Layer 1
Ground Plane
CLDO2 CLDO3 CLDO4 CBYP
CLDO1
LDO2 LDO3 LDO4 BYP EN
LDO1
VIN
CIN
GND
IRQ SDA
VIN GND PWM
SC667
SCL ADI BL1
GND
BL7
BL6
BL5
BL3
Figure 17 -- Recommended PCB Layout
BL2
BL4
Figure 19 -- Layer 2
24
SC667
Serial Interface
The I2C General Specification
The SC667 is a read-write slave-mode I C device and complies with the Philips I2C standard Version 2.1, dated January 2000. The SC667 has twenty-three user-accessible internal 8-bit registers. The I2C interface has been designed for program flexibility, supporting direct format for write operation. Read operations are supported on both combined format and stop separated format. While there is no auto increment/decrement capability in the SC667 I2C logic, a tight software loop can be designed to randomly access the next register independent of which register you begin accessing. The start and stop commands frame the data-packet and the repeat start condition is allowed if necessary.
2
the appropriate 8 bit data byte. Once again, the slave acknowledges and the master terminates the transfer with the stop condition [P]. Combined Format -- Read After the start condition [S], the slave address is sent, followed by an eighth bit indicating a write. The SC667 I2C then acknowledges that it is being addressed, and the master responds with an 8 bit data byte consisting of the register address. The slave acknowledges and the master sends the repeated start condition [Sr]. Once again, the slave address is sent, followed by an eighth bit indicating a read. The slave responds with an acknowledge and the 8 bit data from the previously addressed register; the master then sends a non-acknowledge (NACK). Finally, the master terminates the transfer with the stop condition [P]. Stop Separated Reads Stop-separated reads can also be used. This format allows a master to set up the register address pointer for a read and return to that slave at a later time to read the data. In this format the slave address followed by a write command are sent after a start [S] condition. The SC667 then acknowledges it is being addressed, and the master responds with the 8-bit register address. The master sends a stop or restart condition and may then address another slave. After performing other tasks, the master can send a start or restart condition to the SC667 with a read command. The device acknowledges this request and returns the data from the register location that had previously been set up.
SC667 Limitations to the I2C Specifications
The SC667 only recognizes seven bit addressing. This means that ten bit addressing and CBUS communication are not compatible. The device can operate in either standard mode (100kbit/s) or fast mode (400kbit/s).
Slave Address Assignment
The seven bit slave address is 1110 000x. The eighth bit is the data direction bit. E0h is used for a write operation, and E1h is used for a read operation.
Supported Formats
The supported formats are described in the following subsections. Direct Format -- Write The simplest format for an I2C write is direct format. After the start condition [S], the slave address is sent, followed by an eighth bit indicating a write. The SC667 I2C then acknowledges that it is being addressed, and the master responds with an 8 bit data byte consisting of the register address. The slave acknowledges and the master sends
25
SC667
Serial Interface (continued)
I2C Direct Format Write
S
Slave Address
W
A
Register Address
A
Data
A
P
S - Start Condition W - Write = `0' A - Acknowledge (sent by slave) P - Stop condition
Slave Address - 7-bit Register address - 8-bit Data - 8-bit
I2C Stop Separated Format Read
Register Address Setup Access S Slave Address W A Register Address A P S
S - Start Condition W - Write = `0' R - Read = `1' A - Acknowledge (sent by slave) NAK - Non-Acknowledge (sent by master) Sr - Repeated Start condition P - Stop condition
Master Addresses other Slaves Slave Address B S/Sr
Register Read Access Slave Address RA Data NACK P
Slave Address - 7-bit Register address - 8-bit Data - 8-bit
I2C Combined Format Read
S
Slave Address
WA
Register Address
A Sr
Slave Address
R
A
Data
NACK P
S - Start Condition W - Write = `0' R - Read = `1' A - Acknowledge (sent by slave) NAK - Non-Acknowledge (sent by master) Sr - Repeated Start condition P - Stop condition
Slave Address - 7-bit Register address - 8-bit Data - 8-bit
26
SC667
Register Map(1)
Register Address
00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h
D7
0(2) 0(2) 0(2) 0(2) 0(2) 0(2) 0(2) 0(2) 0(2) 0(2) 0(2) 0(2) 0(2) 0(2) 0(2) 0(2) 0(2) 0(2) AD_CMP AD_O7 AD_R7 AD_F7 0(2)
D6
0(2) 0(2) 0(2) 0(2) 0(2) 0(2) 0(2) 0(2) 0(2) 0(2) 0(2) 0(2) 0(2) 0(2) 0(2) 0(2) 0(2) 0(2)
D5
BL6EN DIS B1FEN B2FEN B3FEN B4FEN B1BEN B2BEN B3BEN B4BEN 0(2) 0(2) 0(2) 0(2) 0(2) ER2_2 TT1_2 TT2_2
D4
BL5EN EN IB1_4 IB2_4 IB3_4 IB4_4 IBT1_4 IBT2_4 IBT3_4 IBT4_4 0(2) 0(2) 0(2) 0(2) GRP1 ER2_1 TT1_1 TT2_1
D3
BL4EN
D2
BL3EN
D1
BL2EN
D0
Description
BL1EN Backlight enable for BL1 -- BL6
X(3) / X(3) / X(3) / BL7EN / Bank enable, plus backlight enable for BL7 BANK4EN BANK3EN BANK2EN BANK1EN IB1_3 IB2_3 IB3_3 IB4_3 IBT1_3 IBT2_3 IBT3_3 IBT4_3 LDO1V3 0(2) LDO3V3 LDO4V3 GRP0 ER2_0 TT1_0 TT2_0 AD_UF AD_O3 AD_R3 AD_F3 IB1_2 IB2_2 IB3_2 IB4_2 IBT1_2 IBT2_2 IBT3_2 IBT4_2 LDO1V2 LDO2V2 LDO3V2 LDO4V2 BANK2 ER1_2 ST1_2 ST2_2 IB1_1 IB2_1 IB3_1 IB4_1 IBT1_1 IBT2_1 IBT3_1 IBT4_1 LDO1V1 LDO2V1 LDO3V1 LDO4V1 BANK1 ER1_1 ST1_1 ST2_1 IB1_0 IB2_0 IB3_0 IB4_0 Fade enable and bank #1 backlight current (4) Fade enable and bank #2 backlight current (4) Fade enable and bank #3 backlight current (4) Fade enable and bank #4 backlight current (4)
IBT1_0 Blink/breathe bank #1 target backlight settings IBT2_0 Blink/breathe bank #2 target backlight settings IBT3_0 Blink/breathe bank #3 target backlight settings IBT4_0 Blink/breathe bank #4 target backlight settings LDO1V0 LDO 1 voltage settings LDO2V0 LDO 2 voltage settings LDO3V0 LDO 3 voltage settings LDO4V0 LDO 4 voltage settings BANK0 Lighting effects assignments, banks & groups ER1_0 ST1_0 ST2_0 Effect rates for group #1 and group #2 Target time and start time for group #1 Target time and start time for group #2
AD_INT AD_SATEN AD_OF AD_O6 AD_R6 AD_F6 AD_O5 AD_R5 AD_F5 AD_O4 AD_R4 AD_F4
CLR_INT AD_AUTO AD_EN ALS function AD_O2 AD_R2 AD_F2 AD_O1 AD_R1 AD_F1 AD_O0 ADC output ADOUT AD_R0 ADC rising threshold ADRISE AD_F0 ADC falling threshold ADFALL Other lighting effects -- auto-dim full or partial, auto-dim enable
ADP_ACT ADP_RATE ADP_EN OLE_EN2 OLE_EN1 OLE_EN0 PWM_BYP
Notes: (1) Reset value for all registers = 00h (2) 0 = always write a 0 to these bits (3) X = no function -- see register 01h description for more details. (4) Registers 02h, 03h, 04h, and 05h serve as the "start" setting for blink/breathe lighting effects.
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Register Map (continued) Definition of Registers and Bits
Backlight Enable Register (00h)
The bits of register 00h are used to enable individual backlight current sinks BL1 through BL6. BL6EN through BL1EN [D5:D0] These bits are used to enable current sinks which control backlight current. When enabled, the current sinks will regulate the backlight current set by the corresponding backlight current register. BANK4EN through BANK1EN [Bits D3:D0] The following bits -- BANK4EN, BANK3EN, BANK2EN, and BANK1EN are used to enable or disable individual backlight banks dependent upon the state of the DIS and EN bits, D5 and D4. These bits provide no function when both DIS and EN are equal to one. BL7EN [Alternate Function for Bit D0] This bit is used to enable the current sink which controls backlight current for backlight BL7. When enabled, the current sink will regulate the backlight current set by the corresponding backlight current register.
DIS = 0 EN = 1 D3=1 enables bank #4 D2=1 enables bank #3 D1=1 enables bank #2 D0=1 enables bank #1 D3=1 disables bank #4 D2=1 disables bank #3 D1=1 disables bank #2 D0=1 disables bank #1 D3=1 does nothing D2=1 does nothing D1=1 does nothing D0=1 enables BL7
Bank Enable Register (01h)
The bits of register 01h are multi-function bits. The function of bits D3 through D0 depend upon the state of bits D5 and D4. Bits D3 through D0 may be used to turn individual banks on and off. An alternate function of bit D0 is used to enable and disable backlight BL7. Figure 20 shows how the function of bits D3 through D0 change according to the state of the DIS bit D5 and the EN bit D4. DIS [Bit D5] When writing to register 01h, if DIS bit D5 = 1 and EN bit D4 = 0, then bits D3 through D0 can each disable one of four banks. When disabling a bank, all associated BLxEN bits are automatically overwritten with a zero. EN [Bit D4] When writing to register 01h, if EN bit D4 = 1 and DIS bit D5 = 0, then bits D3 through D0 can each enable one of four banks. When enabling a bank, all associated BLxEN bits are automatically overwritten with a one.
DIS = 1 EN = 0
Register 01h Bits [D3:D0] (1)
(1) Bit functions are active high only, a zero has no function
DIS = 0 EN = 0
D3=1 does nothing D2=1 does nothing D1=1 does nothing D0=1 does nothing DIS = 1 EN = 1
Figure 20 -- Multi-function Bits of Register (01h)
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Register Map (continued)
Bank #1 Backlight Register (02h)
This register is used to set the current for the backlight LEDs in bank #1 and to enable the lighting effect feature for bank #1. These backlights can be turned off using the backlight enable bits of registers 00h and 01h. Writing the 0mA value into this register will also turn off the backlights, but only if the blink and breathe effects are disabled. B1FEN Bit D5 This bit works in conjunction with the B1BEN bit of register 06h to set a lighting effect for bank #1. Figure 21 shows the lighting effects which are enabled by the combination of B1FEN and B1BEN. When fade is enabled, fading will occur in bank #1 each time the bank #1 current is changed, enabled, or disabled. Blink and breathe functions run in a continuous loop when they are enabled.
B1BEN = 0 B1FEN = 1
IB1_4 through IB1_0 [Bits D4:D0] These bits are used to set the current for the backlight LEDs in bank #1. All bank #1 enabled current sinks will sink the same current as shown in Table 2. Table 2 -- Bank #1 Backlight Current
IB1_4
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IB1_3 IB1_2
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
IB1_1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
IB1_0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Backlight Current (mA)
0 0.05 0.1 0.2 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 23 25
Fade
B1BEN = 1 B1FEN = 0
Blink
Bank #1
No Light Effect
B1BEN = 0 B1FEN = 0
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Breathe
B1BEN = 1 B1FEN = 1
Figure 21 -- Bank #1 Lighting Effect
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Register Map (continued)
Bank #2 Backlight Register (03h)
This register is used to set the current for the backlight LEDs in bank #2 and to enable the lighting effect feature for bank #2. These backlights can be turned off using the backlight enable bits of registers 00h and 01h. Writing the 0mA value into this register will also turn off the backlights, but only if the blink and breathe effects are disabled. B2FEN Bit D5 This bit works in conjunction with the B1BEN bit of register 07h to set a lighting effect for bank #2. Figure 22 shows the lighting effects which are enabled by the combination of B2FEN and B2BEN. When fade is enabled, fading will occur in bank #2 each time the bank #2 current is changed, enabled, or disabled. Blink and breathe functions run in a continuous loop when they are enabled.
B2BEN = 0 B2FEN = 1
IB2_4 through IB2_0 [Bits D4:D0] These bits are used to set the current for the backlight LEDs in bank #2. All bank #2 enabled current sinks will sink the same current as shown in Table 3. Table 3 -- Bank #2 Backlight Current
IB2_4
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IB2_3 IB2_2
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
IB2_1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
IB2_0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Backlight Current (mA)
0 0.05 0.1 0.2 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 23 25
Fade
B2BEN = 1 B2FEN = 0
Blink
Bank #2
No Light Effect
B2BEN = 0 B2FEN = 0
0 1 1
Breathe
1 1 1 1 1 1 1 1 1 1 1 1 1 1
B2BEN = 1 B2FEN = 1
Figure 22 -- Bank #2 Lighting Effect
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Register Map (continued)
Bank #3 Backlight Register (04h)
This register is used to set the current for the backlight LEDs in bank #3 and to enable the lighting effect feature for bank #3. These backlights can be turned off using the backlight enable bits of registers 00h and 01h. Writing the 0mA value into this register will also turn off the backlights, but only if the blink and breathe effects are disabled. B3FEN Bit D5 This bit works in conjunction with the B1BEN bit of register 08h to set a lighting effect for bank #3. Figure 23 shows the lighting effects which are enabled by the combination of B3FEN and B3BEN. When fade is enabled, fading will occur in bank #3 each time the bank #3 current is changed, enabled, or disabled. Blink and breathe functions run in a continuous loop when they are enabled.
B3BEN = 0 B3FEN = 1
IB3_4 through IB3_0 [Bits D4:D0] These bits are used to set the current for the backlight LEDs in bank #3. All bank #3 enabled current sinks will sink the same current as shown in Table 4. Table 4 -- Bank #3 Backlight Current
IB3_4
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IB3_3 IB3_2
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
IB3_1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
IB3_0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Backlight Current (mA)
0 0.05 0.1 0.2 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 23 25
Fade
B3BEN = 1 B3FEN = 0
Blink
Bank #3
No Light Effect
B3BEN = 0 B3FEN = 0
0 1 1
Breathe
1 1 1 1 1 1 1 1 1 1 1 1 1 1
B3BEN = 1 B3FEN = 1
Figure 23 -- Bank #3 Lighting Effect
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Register Map (continued)
Bank #4 Backlight Register (05h)
This register is used to set the current for the backlight LEDs in bank #4 and to enable the lighting effect feature for bank #4. These backlights can be turned off using the backlight enable bits of registers 00h and 01h. Writing the 0mA value into this register will also turn off the backlights, but only if the blink and breathe effects are disabled. B4FEN Bit D5 This bit works in conjunction with the B4BEN bit of register 09h to set a lighting effect for bank #4. Figure 24 shows the lighting effects which are enabled by the combination of B4FEN and B4BEN. When fade is enabled, fading will occur in bank #4 each time the bank #4 current is changed, enabled, or disabled. Blink and breathe functions run in a continuous loop when they are enabled.
B4BEN = 0 B4FEN = 1
IB4_4 through IB4_0 [Bits D4:D0] These bits are used to set the current for the backlight LEDs in bank #4. All bank #4 enabled current sinks will sink the same current as shown in Table 5. Table 5 -- Bank #4 Backlight Current
IB4_4
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IB4_3 IB4_2
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
IB4_1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
IB4_0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Backlight Current (mA)
0 0.05 0.1 0.2 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 23 25
Fade
B4BEN = 1 B4FEN = 0
Blink
Bank #4
No Light Effect
B4BEN = 0 B4FEN = 0
0 1 1
Breathe
1 1 1 1 1 1 1 1 1 1 1 1 1 1
B4BEN = 1 B4FEN = 1
Figure 24 -- Bank #4 Lighting Effect
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Register Map (continued)
Blink/Breathe Bank #1 Target Register (06h)
This register is used to enable the LED blink and breathe lighting effects for bank #1 and set the target backlight current. B1BEN Bit [D5] This bit works in conjunction with the B1FEN bit of register 02h to set a lighting effect for bank #1. Figure 25 shows the lighting effects which are enabled by the combination of B1FEN and B1BEN.
B1BEN = 0 B1FEN = 1
IBT1_4 through IBT1_0 [D4:D0] When lighting effects are enabled, these bits set the target backlight current for bank #1. Target values are shown in Table 6. Table 6 -- Bank #1 Target Backlight Current
IBT1_4 IBT1_3 IBT1_2 IBT1_1 IBT1_0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Bank #1 Target Current (mA)
0 0.05 0.1 0.2 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 23 25
Fade
B1BEN = 1 B1FEN = 0
Blink
Bank #1
No Light Effect
B1BEN = 0 B1FEN = 0
0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Breathe
B1BEN = 1 B1FEN = 1
Figure 25 -- Bank #1 Lighting Effect
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Register Map (continued)
Blink/Breathe Bank #2 Target Register (07h)
This register is used to enable the LED blink and breathe lighting effects for bank #2 and set the target backlight current. B2BEN Bit [D5] This bit, in conjunction with the B2FEN bit, enables blink/ breathe functions for bank #2 as shown in Figure 26.
B2BEN = 0 B2FEN = 1
IBT2_4 through IBT2_0 [D4:D0] When lighting effects are enabled, these bits set the target backlight current for bank #2. Target values are shown in Table 7. Table 7 -- Bank #2 Target Backlight Current
IBT2_4 IBT2_3 IBT2_2 IBT2_1 IBT2_0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Bank #2 Target Current (mA)
0 0.05 0.1 0.2 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 23 25
Fade
B2BEN = 1 B2FEN = 0
Blink
Bank #2
No Light Effect
B2BEN = 0 B2FEN = 0
Breathe
0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
B2BEN = 1 B2FEN = 1
Figure 26 -- Bank #2 Lighting Effect
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Register Map (continued)
Blink/Breathe Bank #3 Target Register (08h)
This register is used to enable the LED blink and breathe lighting effects for bank #3 and set the target backlight current. B3BEN Bit [D5] This bit, in conjunction with the B3FEN bit, enables blink/ breathe functions for bank #3 as shown in Figure 27.
B3BEN = 0 B3FEN = 1
IBT3_4 through IBT3_0 [D4:D0] When lighting effects are enabled, these bits set the target backlight current for bank #3. Target values are shown in Table 8. Table 8 -- Bank #3 Target Backlight Current
IBT3_4 IBT3_3 IBT3_2 IBT3_1 IBT3_0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Bank #3 Target Current (mA)
0 0.05 0.1 0.2 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 23 25
Fade
B3BEN = 1 B3FEN = 0
Blink
Bank #3
No Light Effect
B3BEN = 0 B3FEN = 0
Breathe
B3BEN = 1 B3FEN = 1
Figure 27 -- Bank #3 Lighting Effect
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Register Map (continued)
Blink/Breathe Bank #4 Target Register (09h)
This register is used to enable the LED blink and breathe lighting effects for bank #4 and set the target backlight current. B4BEN Bit [D5] This bit, in conjunction with the B4FEN bit, enables blink/ breathe functions for bank #4 as shown in Figure 28.
B4BEN = 0 B4FEN = 1
IBT4_4 through IBT4_0 [D4:D0] When lighting effects are enabled, these bits set the target backlight current for bank #4. Target values are shown in Table 9. Table 9 -- Bank #4 Target Backlight Current
IBT4_4 IBT4_3 IBT4_2 IBT4_1 IBT4_0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Bank #4 Target Current (mA)
0 0.05 0.1 0.2 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 23 25
Fade
B4BEN = 1 B4FEN = 0
Blink
Bank #4
No Light Effect
B4BEN = 0 B4FEN = 0
Breathe
B4BEN = 1 B4FEN = 1
Figure 28 -- Bank #4 Lighting Effect
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Register Map (continued)
LDO1 Control Register (0Ah)
This register is used to enable LDO1 and set its output voltage level. Bits [D5:D4] These bits are unused and are always zeroes. LDO1V3 through LDO1V0 [D3:D0] These bits set the output voltage of LDO1 as shown in Table 10. Table 10 -- LDO1 Control Codes
LDO1V3
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
LDO2 Control Register (0Bh)
This register is used to enable LDO2 and set its output voltage level. Bits [D5:D3] These bits are unused and are always zeroes. LDO2V2 through LDO2V0 [D2:D0] These bits are used to set the output voltage of LDO2 in accordance with Table 11. Table 11 -- LDO2 Control Codes
VLDO1
OFF 3.3V 3.2V 3.1V 3.0V 2.9V 2.8V 2.7V 2.6V 2.5V 2.4V 2.2V 1.8V 1.7V 1.6V 1.5V
LDO1V2
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
LDO1V1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
LDO1V0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
LDO2V2
0 0 0 0 1 1 1 1
LDO2V1
0 0 1 1 0 0 1 1
LDO2V0
0 1 0 1 0 1 0 1
VLDO2
OFF 1.8V 1.7V 1.6V 1.5V 1.4V 1.3V 1.2V
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Register Map (continued)
LDO3 Control Register (0Ch)
This register is used to enable LDO3 and set its output voltage level. Bits [D5:D4] These bits are unused and are always zeroes. LDO3V3 through LDO3V0 [D3:D0] These bits are used to set the output voltage of LDO3 as shown in Table 12. Table 12 -- LDO3 Control Codes
LDO3V3
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
LDO4 Control Register (0Dh)
This register is used to enable LDO4, set its output voltage level, and provide power for the internal ADC. The ADC will not function without first turning on LDO4. The output of LDO4 is used internally to provide the fullscale reference voltage for the ADC. When the ADC is active, LDO4 also provides a convenient source of power for devices such as ambient light sensors and temperature sensors. Bits [D5:D4] These bits are unused and are always zeroes. LDO4V3 through LDO4V0 [D3:D0] These bits are used to set the output voltage of LDO4 as shown in Table 13. Table 13 -- LDO4 Control Codes
LDO4V3
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
LDO3V2
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
LDO3V1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
LDO3V0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
VLDO3
OFF 3.3V 3.2V 3.1V 3.0V 2.9V 2.8V 2.7V 2.6V 2.5V 2.4V 2.2v 1.8V 1.7V 1.6V 1.5V
LDO4V2
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
LDO4V1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
LDO4V0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
VLDO4
OFF 3.3V 3.2V 3.1V 3.0V 2.9V 2.8V 2.7V 2.6V 2.5V 2.4V 2.2V 1.8V 1.7V 1.6V 1.5V
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Register Map (continued)
Lighting Effects Assignment Register (0Eh)
This register is used to assign the backlight LEDs to four banks, bank #1, bank #2, bank #3, and bank #4. This register is also used to assign the banks to two groups, group #1 and group #2. Group #1 and group #2 are assigned independently to a lighting effect and an effect rate, as described in the next section, Effect Rate Options. GRP1 and GRP0 [D4:D3] These bits are used to assign banks into two groups of independent lighting effects and effect rates. The group assignments are shown in Table 14. Table 14 -- Lighting Effect Assignments
GRP1
0 0 1 1
Effect Rate Options (0Fh)
This register is used to set the effects rate for the fade and breathe effects. Different effect rates may be applied to group #1 and group #2. ER2_2, ER2_1, and ER2_0 [D5:D3] Banks assigned to group #2 will step through settings at the rate shown in Table 16. Table 16 -- Effect Rates for Group #2
ER2_2
0 0 0 0 1 1 1 1
ER2_1
0 0 1 1 0 0 1 1
ER2_0
0 1 0 1 0 1 0 1
Breathe Rate (msstep)
snap to target 4 8 16 24 32 48 64
Fade Rate (msstep)
snap to target 1 2 4 6 8 12 16
GRP0
0 1 0 1
Bank(s) Assigned Group #1
#1 #1 and #2 #1, #2, and #3 #1,# 2, #3, and #4
Bank(s) Assigned to Group #2
#2, #3, and #4 #3 and #4 #4 no banks assigned
BANK2, BANK1, and BANK0 [D2:D0] These bits provide bank assignments for all backlight LEDs. Backlight bank assignments are shown in Table 15. The table shows the backlight pins assigned to each of the four banks, as assigned by the data bits BANK2, BANK1, and BANK0. Table 15 -- Backlight Bank Assignments
BANK2 BANK1 BANK0 Bank #4
BL1 BL1 BL1
ER1_2, ER1_1, and ER1_0 [D2:D0] Banks assigned to group #1 will step through settings at the rate shown in table 17. Table 17 -- Effect Rates for Group #1
ER1_2
0 0 0 0 1 1 1 1
ER1_1
0 0 1 1 0 0 1 1
ER1_0
0 1 0 1 0 1 0 1
Breathe Rate (msstep)
snap to target 4 8 16 24 32 48 64
Fade Rate (msstep)
snap to target 1 2 4 6 8 12 16
Bank #3
BL1 BL2 BL2 BL2
Bank #2
BL1 BL1 - BL2 BL2 BL1 - BL3 BL3 BL3 - BL4 BL3 - BL5
Bank #1
BL1 - BL7 BL2 - BL7 BL3 - BL7 BL3 - BL7 BL4 - BL7 BL4 - BL7 BL5 - BL7 BL6 - BL7
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
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Register Map (continued)
Group #1 Target and Start Times Register (10h)
This register is used to set the duration that the backlights will stay at the start value and at the target value. This feature provides additional customization of the breathe and blink lighting effects. Register 10h will only effect banks that are assigned to group #1. TT1_2, TT1_1, and TT1_0 [D5:D3] These bits set the duration that backlights will stay at the target value. These bits effect only banks assigned to group #1. Target times are given in Table 18. Table 18 -- Target Time (Group #1)
TT1_2
0 0 0 0 1 1 1 1
Group #2 Target and Start Times Register (11h)
This register is used to set the duration that the backlights will stay at the start value and at the target value. This feature provides additional customization of the breathe and blink lighting effects. Register 11h will only effect banks that are assigned to group #2. TT2_2, TT2_1, and TT2_0 [D5:D3] These bits set the duration that backlights will stay at the target value. These bits effect only banks assigned to group #2. Target times are given in Table 20. Table 20 -- Target Time (Group #2)
TT2_2
0 0 0 0 1 1 1 1
TT1_1
0 0 1 1 0 0 1 1
TT1_0
0 1 0 1 0 1 0 1
Target Time (ms)
32 64 256 512 1024 2048 3072 4096
TT2_1
0 0 1 1 0 0 1 1
TT2_0
0 1 0 1 0 1 0 1
Target Time (ms)
32 64 256 512 1024 2048 3072 4096
ST1_2, ST1_1, and ST1_0 [D2:D0] These bits set the duration of time that backlights will stay at the starting value. These bits effect only banks assigned to group #1. Start times are given in Table 19. Table 19 -- Start Time (Group #1)
ST1_2
0 0 0 0 1 1 1 1
ST2_2, ST2_1, and ST2_0 [D2:D0] These bits set the duration that backlights will stay at the starting value. These bits effect only banks assigned to group #2. Start times are given in Table 21. Table 21 -- Start Time (Group #2)
ST2_2
0 0 0 0 1 1 1 1
ST1_1
0 0 1 1 0 0 1 1
ST1_0
0 1 0 1 0 1 0 1
Start Time (ms)
32 64 256 512 1024 2048 3072 4096
ST2_1
0 0 1 1 0 0 1 1
ST2_0
0 1 0 1 0 1 0 1
Start Time (ms)
32 64 256 512 1024 2048 3072 4096
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SC667
Register Map (continued)
ADC Function Register (12h)
This register is used to enable the functions of the ADC and store related status bits. The ADC converts the analog output voltage signal of an ALS (Ambient Light Sense) circuit and stores the digital conversion in the ADC output ADOUT (register 13h). The data may be used to automatically adjust the brightness of bank #1 backlights in response to changes in ambient lighting conditions. AD_CMP [D7] This bit indicates the comparison of ADOUT (register 13h) to both ADRISE (register 14h) and ADFALL(register 15h). When ADOUT exceeds ADRISE, AD_CMP = 1. When ADOUT falls below ADFALL , AD_CMP = 0. AD_INT [D6] This bit is set when the AD_CMP bit [D7] changes state. If the AD_SATEN [D5] bit is set, AD_INT bit [D6] may also be used to indicate an overflow or underflow in ADOUT (register 13h). This bit is cleared when ADC function register (12h) is read, or when writing INT_CLR bit [D2] equal to one. AD_SATEN [D5] This bit, when set, allows an underflow or overflow to generate an interrupt which sets the AD_INT bit [D6]. When AD_SATEN = 1, an overflow or underflow condition in register 13h will set the AD_INT bit. AD_OF [D4] This bit indicates an overflow condition in register 13h. This bit is set to one whenever ADOUT > F8h. AD_UF [D3] This bit indicates an underflow condition in register 13h. This bit is set to one whenever ADOUT < 08h. INT_CLR [D2] Writing a one to this bit automatically resets bit AD_INT to zero. INT_CLR resets itself and will always read as zero. AD_AUTO [D1] When the AD_AUTO bit is high, the contents of the ADOUT, ADRISE, and ADFALL registers are compared and used to control the brightness of the bank #1 backlights. ADOUT is compared with two threshold values contained in registers ADRISE and ADFALL. If ADOUT becomes greater than ADRISE, bank #1 will change to the bank #1 target backlight setting of register 06h. If ADOUT becomes less than ADFALL, bank #1 will change to the bank #1 backlight setting of register 02h. When the AD_AUTO bit is low, the comparison of ADOUT to ADRISE and ADFALL is disabled so that bank #1 does not react to changes in the value of ADOUT, ADRISE, or ADFALL. AD_EN [D0] When the AD_EN bit is high, the ADC is activated and the results of each conversion are stored in ADOUT (register 13h). The functions of the AD_AUTO and AD_EN bits are shown in Table 22. Table 22 -- ALS Function Enable Bits
AD_AUTO AD_EN
0 0
Comments
ADC is disabled. Bank #1 will not change brightness with ambient conditions. ADC is enabled. ADC output is stored in the ADOUT register. Bank #1 does not respond to the ADOUT value. ADC is disabled. Bank #1 current is set to the start or target current. ADOUT is compared to ADRISE and ADFALL registers. A new value may be written to ADOUT via the I2C interface. ADC is enabled. Bank #1 current is set to the start or target current. ADOUT is compared to ADRISE and ADFALL registers.
0
1
1
0
1
1
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SC667
Register Map (continued)
The ALS comparator functions are shown in Table 23. Table 23 -- ALS Comparator Function(1)
Conditions
ADOUT > ADRISE ADOUT < ADFALL ADFALL ADOUT ADRISE
ADC Output and Threshold Register (13h)
This register contains the value ADOUT which is compared with ADRISE and ADFALL. The contents of ADOUT may originate automatically from the ADC, when the AD_EN bit is a logic one. Alternatively, ADOUT may be written to the register via the I2C interface when the AD_EN bit is a logic zero. When AD_EN = 1, the ADC receives its analog voltage input signal from the external photo-detector circuit connected to the ADI pin. VADI is then converted into digital and stored as the 8 bit word ADOUT. The reference voltage for the ADC is provided internally by the output of LDO4 (VLDO4). When the voltage VADI is equal to VLDO4 , the ADC is at full-scale value FFh, and ADOUT will equal FFh. When using an external photo-detection circuit, the ADC requires the LDO output voltage VLDO4 to remain constant. VLDO4 can drop-out if the supply voltage becomes too low. VLDO4 should be set to a value sufficiently low to guard against drop-out. To prevent drop-out, the maximum LDO4 output setting should be limited to: VLDO4(MAX) = VIN(MIN) - [1.33 x ILDO4(MAX)], where VIN(MIN) is the minimum battery voltage and ILDO4(MAX) is the maximum load current of LDO4. LDO4 load current includes current to the external photo-detection circuit. AD_O7 through AD_O0 [D7:D0] These are the 8 bits of ADOUT. AD_O7 [D7] is the Most Significant Bit (MSB), and AD_O0 [D0] is the Least Significant Bit (LSB). Binary weights of these bits are shown in Table 24. Table 24 -- ADOUT Bits [D7:D0]
Name
AD_O7 AD_O6 AD_O5 AD_O4 AD_O3 AD_O2 AD_O1 AD_O0
ADOUT Effect on Bank #1
Brightness changes to target value Brightness changes to start value Brightness does not change Hysteresis between the rising and falling thresholds is disabled and . . . ADFALL has no effect on brightness ADO > ADRISE brightness changes to target value ADO < ADRISE brightness changes to start value ADO = ADRISE brightness does not change
ADFALL ADRISE
Note: 1) When AD_AUTO bit is high.
The state diagram of Figure 29 shows how the ADC is used to change the brightness of backlight bank #1. No automatic change in brightness occurs when AD_AUTO = 0.
ADOUT < ADRISE AD_AUTO = 1 or 0
Bank #1 Brightness
= Value of Register 02h
AD_AUTO = 1 ADOUT < ADFALL AD_AUTO = 0 ADOUT < ADFALL
AD_AUTO = 0 ADOUT > ADRISE
AD_AUTO = 1 ADOUT > ADRISE
Bit
D7 D6 D5 D4 D3 D2 D1 D0
Binary Weight
1/2 1/4 1/8 1/16 1/32 1/64 1/128 1/256
Bank #1 Brightness
= Value of Register 06h
ADOUT > ADFALL AD_AUTO = 1 or 0
Figure 29 -- ADC function at Bank #1 Brightness
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SC667
Register Map (continued)
To calculate the voltage at the ADC input, the weights of only the bits set to one are summed together and multiplied by the voltage provided by LDO4. The result is equal to the analog voltage applied to the ADI pin. For example, if the value of register 13h reads AD OUT = 01111111, and VLDO4 = 2.8V, the ADC input is at: 2.8 x (4-1 + 8-1 + 16-1 + 32-1 + 64-1 + 128-1 + 256-1) = 1.38V. sink is floating, the ADP_EN bit is cleared automatically. Any write operations to change the following bit combinations in register 01h will also cause bank #1 to resume the original setting:
* * *
DIS = 1, EN = 0, BANK1EN = 1 DIS = 0, EN = 1, BANK1EN = 1 DIS = 1, EN = 1, BANK1EN = 1
ADC Rising Threshold (14h)
This register contains the value ADRISE. When ADOUT rises above ADRISE and AD_AUTO = 1, backlight bank #1 changes to the target value in the bank #1 target register (06h). AD_R7 through AD_R0 [D7:D0] These are the 8 bits of ADRISE. AD_R7 is the MSB, and AD_R0 is the LSB.
ADP_ACT Bit D6 This bit is a flag. A logic one indicates that ADP has been activated. Once activated, the ADP is limiting the backlight current. This flag bit is reset when ADP_EN = 0, or when any bank#1 current sink is floating, or by writing any of the following bit combinations in register 01h:
ADC Falling Threshold (15h)
This register contains the value ADFALL. When ADOUT falls below ADFALL and AD_AUTO = 1, backlight bank #1 changes to the starting value in the bank #1 register (02h). AD_F7 through AD_F0 [D7:D0] These are the 8 bits of ADFALL. AD_F7 is the MSB, and AD_F0 is the LSB.
* * *
DIS = 1, EN = 0, BANK1EN = 1 DIS = 0, EN = 1, BANK1EN = 1 DIS = 1, EN = 1, BANK1EN = 1
ADP_RATE Bit D5 This bit sets the time that elapses before backlight current reduces after ADP activates. A logic one delays reduction of current for 4ms. A logic zero delays reduction of current for 256s. When a reduction in bank #1 backlight current becomes necessary, the first step change is delayed for 4ms (logic one) or 256s (logic zero). If bank #1 continues to need a current reduction after the delay time has elapsed, the brightness setting is lowered by one step. If further reductions in current are needed, the second and all subsequent reductions occur at a faster rate equal to1/4 of the initial delay time. Further reductions in current will stop when the backlight accuracy and matching have normalized. When 4ms is selected, the 1st delay = 4ms, and the 2nd and all subsequent delays = 1ms. When 256s is selected, the 1st delay = 256s, and the 2nd and all subsequent delays = 64s.
ADP and OLE Functions (16h)
ADP (Automatic Drop-out Protection) and OLE (Other Lighting Effects) are controlled with this register. ADP applies to bank #1 only. ADP ensures current matching in the LEDs by responding to a low battery voltage. ADP limits the maximum backlight current to a level which ensures that backlight LEDs maintain matched currents. The ADP feature also prevents the ripple on a low battery from inducing flicker in the LEDs. As the battery voltage gradually proceeds lower, ADP gradually dims the backlights. The normal backlight brightness is restored after the battery is recharged by writing a logic zero to the ADP_EN bit. Bank #1 will try to resume the original backlight current setting whenever ADP_EN = 0. Also, if any bank #1 current
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SC667
Register Map (continued)
ADP_EN Bit D4 This bit enables the ADP function. ADP is enabled when this bit is a logic one. ADP is disabled when this bit is a logic zero. OLE_EN2 through OLE_EN0 Bits [D3:D1] These bits enable Other Lighting Effects (OLE), including the auto-dim full and auto-dim partial, as shown in Table 25. Auto-dim functions are described in detail in the Applications Information section. Table 25 -- OLE Bits
OLE_EN2 OLE_EN1 OLE_EN0
0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Reserved (no effects)
PWM_BYP Bit D0 When this bit is a logic zero, the PWM pin functions normally. When this bit is a logic one, the PWM pin is disabled, so that a high or low on the PWM pin has no effect.
Lighting Effect
Reserved (no effects) Auto-dim full (group #1) Auto-dim partial (group #1)
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SC667
Outline Drawing -- MLPQ-UT-20 3x3
A D B DIM A A1 A2 b D D1 E E1 e L N aaa bbb DIMENSIONS INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX .020 .024 0.50 0.60 .000 .002 0.00 0.05 (.006) (0.152) .006 .008 .010 0.15 0.20 0.25 .114 .118 .122 2.90 3.00 3.10 .061 .067 .071 1.55 1.70 1.80 .114 .118 .122 2.90 3.00 3.10 .061 .067 .071 1.55 1.70 1.80 .016 BSC 0.40 BSC .012 .016 .020 0.30 0.40 0.50 20 20 .003 0.08 .004 0.10
PIN 1 INDICATOR (LASER MARK)
E
A2 A aaa C A1 e LxN E/2 E1 2 1 N D/2 bxN bbb NOTES: 1. 2. 3. CAB D1 C SEATING PLANE
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DAP IS 1.90 x 1.90mm.
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SC667
Land Pattern -- MLPQ-UT-20 3x3
K R DIM (C) Z C G H K P R X Y Z (.114) .083 .067 .067 .016 .004 .008 .031 .146 DIMENSIONS INCHES MILLIMETERS (2.90) 2.10 1.70 1.70 0.40 0.10 0.20 0.80 3.70
H
G
Y X
P
NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD SHALL BE CONNECTED TO A SYSTEM GROUND PLANE. FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR FUNCTIONAL PERFORMANCE OF THE DEVICE.
3.
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SC667
(c) Semtech 2010 All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. Semtech assumes no responsibility or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper installation, repair or improper handling or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified range. SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFESUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF SEMTECH PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE UNDERTAKEN SOLELY AT THE CUSTOMER'S OWN RISK. Should a customer purchase or use Semtech products for any such unauthorized application, the customer shall indemnify and hold Semtech and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs damages and attorney fees which could arise. Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805) 498-2111 Fax: (805) 498-3804 www.semtech.com
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